1. Field of the Invention
The present invention relates to improvement in a circuit configuration technique of a circuit for detecting and correcting a central level required at a time of demodulation of an FSK (Frequency Shift Keying) signal.
2. Background of the Invention
In general, a demodulated signal of an FSK signal involves an error in its center level for many causes such as an error in transmission frequency, an error in the local oscillation frequency in a receiver, a frequency error in a frequency discriminator, and a drift in a direct current circuit system. A variety of methods have, therefore, been proposed and used to detect the center level of a demodulated signal and/or to correct an error in center level . Representative examples of such methods include: (1) Two holders are arranged to hold a positive and negative peak value of binary format data of a demodulated signal, respectively, and from the mean value of outputs from the two holders, a center level is determined. (2) A dead zone circuit is arranged for a DC current to be input to a baseband-signal-processing DC current system, and a positive and negative width of a demodulated baseband signal is set to conform with a dead zone voltage width of the dead zone circuit. With the dead zone circuit arranged and set as mentioned above, no output is produced from the dead zone circuit when there is no error in center level, but when there is an error in center level, an output corresponding to the error is produced from the dead zone circuit. Accordingly, the error in the center level is determined by relying upon the magnitude of the output from the dead zone circuit. (3) A center level is determined by integrating a bit synchronizing signal, which exists at the head of a packet signal, over a 2-bit length. (4) A bit synchronizing signal is sampled twice at an interval of a bit length (1 baud/sec) to obtain sample values. (5) Developing the method (1) further, two holders are arranged to hold a positive and negative peak value of binary format data of a demodulated signal, respectively, and a further holder is arranged to hold the 1/2  value (shift width voltage) of the difference between the positive and negative peak values. When bit “1” or bit “0” occurs successively in the binary format data, the shift width voltage is added to the binary format data or is subtracted from the binary format data to determine the center level of the demodulated signal.
In these methods, however, there are the following drawbacks. That is, in the respective methods, since the center level is first obtained in an initial stage of signal reception start, an error of the center level can be corrected by using the center level thus obtained. However, a problem occurs thereafter. When a center level has fluctuated due to a frequency fluctuation or the like, it is impossible to follow this fluctuation in the methods (1), (3) and (4). In the method (2), when a center level has fluctuated in a state where a signal is frequently fluctuating between “1” and “0”, which side of the dead zone band has overflowed can be found so that an error of a center level can be detected immediately. However, when the signal remains “1” or “0” for a long time period, detection can be made when “1” or “0” shifts in an overflowing direction from the dead zone band, but in case that the signal shifts in a reverse direction thereto, detection can not be made except that the shifting exceeds the dead zone bandwidth. In the method (5), the drawbacks found in the above-described methods can be solved, but another problem occurs. The problem also occurs in the method (1), and it is a problem due to discharging of a hold voltage inevitably caused by using an analog circuit. Therefore, the method (5) can not be applied except for a time range where an influence of the discharging can be disregarded.
In order to solve the above problem, an object of the present invention is to construct a circuit where in a demodulation of an FSK signal, not only at a time of communication start but also even in a case that “1” or “0” of the FSK demodulation signal continues for a long time, a center level can always be detected and an error, if any, can be corrected.